Semiconductor package

ABSTRACT

A semiconductor package includes a trace molding compound layer and a chip molding compound layer. The trace molding compound layer has a first surface and a second surface, wherein the trace molding compound layer encapsulates a plurality of traces and studs between the first and second surface. The chip molding compound layer has a first surface and a second surface, wherein the chip molding compound layer encapsulates a semiconductor chip between the first and second surface of the chip molding compound layer. The chip molding compound layer is disposed on the trace molding compound layer, the second surface of the chip molding compound layer adheres to the first surface of the trace molding compound layer, and the chip molding compound layer and the trace molding compound layer comprise substantially the same molding compound material.

This is a divisional application of U.S. application Ser. No.13/127,061, filed May 2, 2011, now in a state of allowability. Thisapplication claims the benefit of U.S. provisional application Ser. No.61/112,207, filed Nov. 7, 2008, and claims the benefit of a PatentCooperation Treaty application Serial No. PCT/SG2009/000408, filed Nov.6, 2009, the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to a semiconductor package, and moreparticularly to a semiconductor package with enhanced routing designflexibility.

2. Description of the Related Art

Referring to FIG. 1, a conventional Quad-Flat Pack (QFN) semiconductorpackage is shown. The semiconductor package 10 includes a chip 12, alead frame 14, a plurality of wires 16, a chip base 18, a chipsupporting studs 20 and an adhesive 24. The lead frame 14 located on theperipheral of the semiconductor package 10 is exposed from the bottomsurface of the semiconductor package 10 to be used as an I/O contact ofthe semiconductor package 10. The chip 12 is disposed on the chip base18. The chip base supporting stud 20 supports the chip base 18 toenhance the structural strength of the semiconductor package 10.

However, the wires 16, extended around the semiconductor package 10, aretoo long and exposed to the risk of short-circuiting. Besides, the leadframe 14, being used as an I/O contact, can only be disposed on theperipheral of the semiconductor package 10, hence limiting the number ofthe I/O contacts of the semiconductor package 10. Consequently,increasing the number of I/O contacts substantially increases the sizeof the semiconductor package. Moreover, the lead frame 14 being used asan I/O contact is exposed in the air, and is susceptible to the erosionby the environment.

SUMMARY OF THE INVENTION

The invention is directed to a semiconductor package and a method formanufacturing the semiconductor package and a trace substrate and amethod for manufacturing the trace substrate. The semiconductor packageincludes a plurality of trace pads, a plurality of wires, a plurality ofconductive studs and a molding compound. The trace pads can be disposednear the chip, so that the wire connects the chip and the trace pad viaa shortest distance to reduce the risk of wire-crossing andshort-circuiting. Besides, the trace pads of the semiconductor packageare not limited to be disposed on the peripheral of the semiconductorpackage, so the number of the I/O contacts of the semiconductor packagecan be greatly increased. Moreover, the trace pads and the conductivestuds are protected inside the molding compound, and will not be erodedeasily.

According to a first aspect of the present invention, a semiconductorpackage is provided. The semiconductor package includes a tracesubstrate, a chip, a plurality of wires and a chip molding compound. Thetrace substrate includes a plurality of traces, a plurality ofconductive studs, a plurality of traces pads and a trace moldingcompound. The trace pads are disposed on the trace. The conductive studscorrespondingly are formed on the traces, the trace pads and theircorresponding conductive studs are separated by a distance and arrangedalong an extending direction of the trace. The trace molding compoundencapsulates the conductive studs and the trace, and exposes aconductive stud surface of each conductive stud and a trace surface ofeach trace. The chip is disposed on the surface of the trace substratewhich exposes the trace upper surface. The wires electrically connectthe chip and the trace pads. The chip molding compound is disposed onthe trace substrate. The chip molding compound encapsulates the chip andthe wire.

According to a second aspect of the present invention, a trace substrateis provided. The trace substrate is for disposing a chip. The tracesubstrate includes a plurality of traces, a plurality of conductivestuds, a plurality of traces pads and a trace molding compound. Theconductive studs correspondingly are formed on the traces. The tracepads are correspondingly disposed on the traces, wherein the trace padsand their corresponding conductive studs are separated by a distancealong an extending direction of the traces. The trace molding compoundencapsulates the conductive studs and the traces, and exposes aconductive stud surface of each conductive stud and a trace surface ofeach trace.

According to a third aspect of the present invention, a method formanufacturing semiconductor package is provided. The manufacturingmethod includes the following steps. A carrier is provided. A pluralityof traces is formed on a lower surface of the carrier. A plurality oftraces pads is formed on the traces. A plurality of conductive studs isformed on the trace, wherein the trace pads and their correspondingconductive studs are separated by a distance along an extendingdirection of the trace. The conductive studs and the traces areencapsulated by a trace molding compound. The bottom surface of thetrace molding compound is grinded to expose a conductive stud surface ofeach conductive stud. The carrier is removed to expose a trace surfaceof each trace so that conductive studs, the trace and the trace moldingcompound together form a trace substrate. A chip is disposed on thesurface of the trace substrate which exposes the trace upper surface.The chip and the trace upper surface are electrically connected by aplurality of wires. A chip molding compound is formed on the tracesubstrate, wherein the chip molding compound encapsulates the chip andthe wire.

According to a fourth aspect of the present invention, a method formanufacturing trace substrate is provided. The manufacturing methodincludes the following steps. A carrier is provided. A plurality oftraces is formed on a lower surface of the carrier. A plurality ofconductive studs is formed on the traces. A plurality of traces pads isformed on the trace, wherein the trace pads and their correspondingconductive studs are separated by a distance along an extendingdirection of the trace. The conductive studs and the trace areencapsulated by a trace molding compound. The bottom surface of thetrace molding compound is grinded to expose a conductive stud surface ofeach conductive stud. The carrier is removed to expose a trace surfaceof each trace.

The invention will become apparent from the following detaileddescription of the preferred but non-limiting embodiments. The followingdescription is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a generally known semiconductor package;

FIG. 2A shows a semiconductor package according to a first embodiment ofthe invention;

FIG. 2B shows a semiconductor package according to another embodiment ofthe invention;

FIGS. 3A-3J show processes for manufacturing the semiconductor packageof FIG. 2A;

FIG. 4 shows a method flowchart for manufacturing semiconductor packageaccording to a first embodiment of the invention;

FIG. 5 shows a semiconductor package according to a second embodiment ofthe invention;

FIGS. 6A-6C show processes for manufacturing the semiconductor packageof FIG. 5;

FIG. 7 shows a method flowchart for manufacturing semiconductor packageaccording to a second embodiment of the invention;

FIG. 8 shows a semiconductor package according to a third embodiment ofthe invention;

FIG. 9 shows a method flowchart for manufacturing semiconductor packageaccording to a third embodiment of the invention;

FIG. 10 shows a semiconductor package of the third embodiment with achip base supporting stud;

FIG. 11 shows a semiconductor package according to a fourth embodimentof the invention;

FIG. 12 shows a method flowchart for manufacturing semiconductor packageaccording to a fourth embodiment of the invention;

FIG. 13 shows a semiconductor package of the present embodiment of theinvention with a plurality of trace supporting studs;

FIG. 14 shows a semiconductor package according to a fifth embodiment ofthe invention;

FIG. 15 shows a method flowchart for manufacturing semiconductor packageaccording to a fifth embodiment of the invention;

FIG. 16 shows a semiconductor package of the present embodiment of theinvention with an insulation layer being formed during the manufacturingprocess;

FIG. 17 shows a semiconductor package according to a sixth embodimentthe invention;

FIG. 18 shows a method flowchart for manufacturing semiconductor packageaccording to a sixth embodiment of the invention;

FIG. 19 shows a semiconductor package according to a seventh embodimentof the invention;

FIG. 20 shows a method flowchart for manufacturing semiconductor packageaccording to a seventh embodiment of the invention;

FIG. 21 shows a semiconductor package according to another embodiment ofthe invention;

FIG. 22 shows a bottom view of the semiconductor package of FIG. 2A;

FIG. 23 shows a bottom view of a semiconductor package according to aneighth embodiment of the invention;

FIG. 24 shows a semiconductor package according to a ninth embodiment ofthe invention; and

FIG. 25 shows a semiconductor package according to a tenth embodiment ofthe invention.

DETAILED DESCRIPTION OF THE INVENTION

A number of preferred embodiments are disclosed below for elaboratingthe invention. However, the disclosures of the embodiments below andtheir accompanied drawings are for exemplification only, not forlimiting the scope of protection of the invention. Moreover, secondaryelements are omitted in the embodiments below for highlighting thetechnical features of the invention.

First Embodiment

Referring to FIG. 2A, a semiconductor package according to a firstembodiment of the invention is shown. The semiconductor package 200includes a trace substrate 202, a chip 204, a plurality of wires 206,preferably gold wire, a chip molding compound 208, preferably moldingcompound and an adhesive 236, preferably polymer epoxy. The tracesubstrate 202 includes a plurality of traces 210, preferably coppertraces, a plurality of trace pads 248, preferably copper pads with goldfinishing, a plurality of conductive studs 216, preferably copper studs,and a trace molding compound 218, preferably molding compound.

Each trace 210 has a trace lower surface 212 and a trace upper surface214 opposite to each other. The trace pads 248 are formed on the traceupper surface 214, and the conductive studs 216 are formed on the tracelower surfaces 212. The trace molding compound 218 encapsulates theconductive studs 216 and the traces 210, and exposes a conductive studlower surface 234 of each conductive stud 216 and the trace uppersurface 214. The conductive stud lower surface 234 and the trace uppersurface 214 are facing opposite directions.

Preferably, the traces 210, the trace pads 248 and the conductive studs216 are made from copper and preferably formed by electroplating.Preferably, the trace upper surface 214, the trace pads 248 and theconductive stud lower surface 234 are further coated with electrolessnickel/electroless palladium/immersion gold (ENEPIG) for surfaceprotection and enhancing its bondability with another component.

In the present embodiment of the invention, the trace pads 248 are notoverlapping to the conductive studs 216. That is, the trace pads 248 andthe conductive studs 216 that are disposed on the same trace 210 areseparated by a distance along an extending direction (the horizontaldirection illustrated in FIG. 2A) of the traces 210.

The trace pads 248 are disposed near the chip 204, so that the wire 206connects the chip 204 and the trace pads 248 via a shortest distance toavoid the wires 206 crossing and short-circuited. Furthermore, shorterwire length reduces cost of manufacturing.

As indicated in FIG. 2A, the trace pads 248 of the semiconductor package200 are no more limited to be disposed on the peripheral of thesemiconductor package 200, and preferably, be disposed near the chip204. Preferably, the conductive studs are also disposed within the tracesubstrate 202. Thus, the number of the I/O contacts of the semiconductorpackage 200 can be greatly increased. Moreover, the trace pads 248 andthe conductive studs 216 are protected inside the molding compound 208,and will not be eroded easily.

Preferably, the traces 210 and the conductive studs 216 are formed byelectroplating, and in comparison to the generally known etched leadframe, the traces 210 and the conductive studs 216 can achieve smallerfeature sizes and be disposed closer to one another within the tracesubstrate. Thus, the semiconductor package 200 of the present embodimentof the invention is conformed to the trend of lightweight, compactnessand slimness.

In the present embodiment of the invention, the distance from theconductive studs 216 to the lateral side 222 of the trace moldingcompound 218 is smaller than the distance from the trace pads 248 to thelateral side 222 so as to form a fan-out semiconductor package.

Despite the semiconductor package 200 of the present embodiment of theinvention is exemplified by a fan-out semiconductor package, thesemiconductor package of the invention can also be a fan-insemiconductor package. Referring to FIG. 2B, a semiconductor packageaccording to another embodiment of the invention is shown. Thesemiconductor package 240 is a fan-in the semiconductor package, and thedistance from the conductive studs 216 to the lateral side 222 of thetrace molding compound 218 is larger than the distance from the tracepads 248 to the lateral side 222 of the trace molding compound 218. Thatis, the distance from the conductive studs 216 to the lateral side 222of the trace molding compound 218 is larger than the distance from thetrace pads 248 to the lateral side 222 of the trace molding compound 218so as to form a fan-in structure.

Return to FIG. 2A, the chip 204 is fixed on the trace substrate 202 withan adhesive 236. In FIG. 2A, the adhesive 236 can be a conductive or aninsulating material. When the chip is disposed on a conductive chip basesuch as the chip base 302 of FIG. 8, the adhesive 236 is preferably madefrom an insulating material.

The wire 206 electrically connects 204 and the trace pads 248. The tracemolding compound 218 has a first insulative surface 218 s 1 and a secondinsulative surface 218 s 2 opposite to the first insulative surface 218s 1. The chip molding compound 208 has a first surface 208 s 1 and asecond surface 208 s 2 opposite to the first surface 208 s 1. The secondsurface 208 s 2 of the chip molding compound 208 adjoins on the firstinsulative surface 218 s 1 of the trace molding compound 218 to form aninterface 218 i between the second surface 208 s 2 of the chip moldingcompound 208 and the first insulative surface 218 s 1 of the tracemolding compound 218. The traces 210 encapsulate the chip 204, theadhesive 236 and the wire 206.

The detailed processes of the method for manufacturing the semiconductorpackage of FIG. 2A are disclosed below. Referring to FIGS. 3A-3J andFIG. 4. FIGS. 3A-3J show processes for manufacturing the semiconductorpackage of FIG. 2A. FIG. 4 shows a method flowchart for manufacturingsemiconductor package according to a first embodiment of the invention.

Firstly, the method begins at step S402 as indicated in FIG. 3A, acarrier 228 is provided.

Next, the method proceeds to step S404 as indicated in FIG. 3B, aplurality of traces 210 and a plurality of trace pads 248 are formed ona carrier lower surface 230 of the carrier 228 preferably byelectroplating. Each trace 210 has a trace lower surface 212 and a traceupper surface 214 which are opposite to each other, wherein the tracepads 248 are formed on the trace upper surface 214.

Then, the method proceeds to step S406 as indicated in FIG. 3C, aplurality of conductive studs 216 is formed on the trace lower surface212 preferably by electroplating.

After that, the method proceeds to step S408 as indicated in FIG. 3D,the conductive studs 216 and the traces 210 are encapsulated by thetrace molding compound 218.

Following that, the method proceeds to step S410 as indicated in FIG.3E, the bottom surface 232 (illustrated in FIG. 3D) of the trace moldingcompound 218 is preferably grinded to expose the lower surface 234 ofeach conductive stud.

Afterwards, the method proceeds to step S412 as indicated in FIG. 3F,the carrier 228 of FIG. 3E is removed preferably by etching to exposethe trace upper surface 214 and the trace pads 248, so that theconductive studs 216, the traces 210 and the trace molding compound 218together form a trace substrate 202.

Then, the method proceeds to step S414 as indicated in FIG. 3G, anadhesive 236 fixes the chip 204 on the surface of the trace substrate202 which exposes the trace upper surface 214.

After that, the method proceeds to step S416 as indicated in FIG. 3H,the chip 204 and the trace pads 248 are electrically connected by aplurality of wires 206.

Following that, the method proceeds to step S418 as indicated in FIG.3I, the chip molding compound 208 is formed on the trace moldingcompound 218, wherein the chip molding compound 208, preferably bymolding process, encapsulates the chip 204, the adhesive 236 and thewire 206.

Lastly, the method proceeds to step S420 as indicated in FIG. 3J, thechip molding compound 208 and the trace substrate 202 are divided alonga cutting path P, preferably by dicing, to form a plurality ofsemiconductor packages 240.

Second Embodiment

Referring to FIG. 5, a semiconductor package according to a secondembodiment of the invention is shown. In the second embodiment, the samedesignations are used for elements similar to the first embodiment, andare not repeated here. The semiconductor package 300 of the secondembodiment differs with the semiconductor package 200 of the firstembodiment in that the semiconductor package 300 includes a chip base302, preferably formed from copper.

The detailed processes of the method for manufacturing the semiconductorpackage of FIG. 5 are disclosed below. Referring to FIGS. 6A-6C and FIG.7. FIGS. 6A-6C show processes for manufacturing the semiconductorpackage of FIG. 5. FIG. 7 shows a method flowchart for manufacturingsemiconductor package according to a second embodiment of the invention.

As steps S702-S704 being similar to steps S402-S404 of FIG. 4 are notrepeated here, the following elaboration starts with step S706.

Next, the method proceeds to step S706 as indicated in FIG. 6A, aplurality of chip bases 302 is formed on the carrier lower surface 230of the carrier 228, preferably by electroplating and preferably formedtogether with the traces.

Then, the method proceeds to step S708, a plurality of conductive studs216 is formed on the trace lower surface 212, wherein step S708 beingsimilar to step S406 of FIG. 4 is not repeated here.

After that, the method proceeds to step S710 as indicated in FIG. 6B,the conductive studs 216, the traces 210 and the chip base 302 areencapsulated by the trace molding compound 218, preferably by moldingprocess.

Afterwards, the method proceeds to steps S712-S714, the bottom surfaceof the trace molding compound 218 is preferably grinded, and the carrier228 of FIG. 6A is removed, preferably by etching. Step S712-S714 beingsimilar to steps S410-S412 of FIG. 4 are not repeated here.

Lastly, the method proceeds to step S716 as indicated in FIG. 6C, theadhesive 236 is used for fixing the chip 204 on the upper surface 250 ofthe chip base 302.

The following steps S718-S722 being similar to the steps S416-S420 ofFIG. 4 are not repeated here.

Third Embodiment

Referring to FIG. 8, a semiconductor package according to a thirdembodiment of the invention is shown. In the third embodiment, the samedesignations are used for elements similar to the second embodiment, andare not repeated here. The semiconductor package 400 of the thirdembodiment differs with the semiconductor package 300 of the secondembodiment in that the semiconductor package 400 further includes aplurality of chip base supporting studs 402, preferably formed fromcopper.

Also, referring to FIG. 9, a method flowchart for manufacturingsemiconductor package according to a third embodiment of the inventionis shown. As steps S902-S906 being similar to the steps S702-S706 ofFIG. 7 are not repeated here, the following elaboration starts with stepS908.

Also, referring to FIG. 10, a semiconductor package of the thirdembodiment with a chip base supporting stud is shown. In step S908, aplurality of chip base supporting stud 402 is formed on the lowersurface 404 of the chip base 302, preferably by electroplating andpreferably formed together with the conductive studs.

The following steps S910-S914 being similar to steps S708-S712 of FIG. 7and are not repeated here. Particularly, in step S912, the trace moldingcompound 218 further encapsulates the chip base supporting studs 402,preferably by molding process.

The chip base supporting studs 402 can be connected to an externalcircuit, such as the dummy pad of a circuit board, for enhancing thebond ability between the semiconductor package and the external circuitand increasing the reliability. Preferably, the wires also electricallyconnect the chip to the chip base supporting studs via the chip base,and subsequently the chip base supporting studs are further connected toan external circuit, such as a ground pad of a circuit board forgrounding purpose.

The following steps S916-S924 being similar to steps S714-S722 of FIG. 7are not repeated here.

Fourth Embodiment

Referring to FIG. 11, a semiconductor package according to a fourthembodiment of the invention is shown. In the fourth embodiment, the samedesignations are used for elements similar to the third embodiment, andare not repeated here. The semiconductor package 500 of the fourthembodiment differs with the semiconductor package 400 of the thirdembodiment in that the semiconductor package 500 is a fan-out structureand further includes a plurality of trace supporting studs 502,preferably formed from copper and preferably formed together with theconductive studs.

As indicated in FIG. 11, the trace supporting studs 502 and the tracepads 248 are overlapped so as to increase the rigidity of the traces210. To put it in a greater detail, when the wires 206 are wire-bondedon the trace pads 248 of the traces 210, due to the trace supportingstuds 502 disposed on the semiconductor package 500, the wires 206 cansupport the traces 210 to resist the force applied by a wiring toolduring the process of wire-bonding to avoid the traces 210 beingoverbent and deformed to such an extent that the wires 206 cannot beconnected to the trace pads 248.

Also, referring to FIG. 12, a method flowchart for manufacturingsemiconductor package according to a fourth embodiment of the inventionis shown. As steps S102-S108 being similar to steps S902-S908 of FIG. 9are not repeated here, the following elaboration starts with step S110.

Also, referring to FIG. 13, a semiconductor package of the presentembodiment of the invention with a plurality of trace supporting studsis shown. In step S110, a plurality of trace supporting studs 502 isformed on the trace lower surface 212. Alternatively, the plurality oftrace supporting studs 502 can also be formed in step 106 together withthe conductive studs.

The following steps S112-S116 being similar to steps S910-S914 of FIG. 9are not repeated here. Particularly, in step S114, the trace moldingcompound 218 further encapsulates the trace supporting studs 502,preferably by molding process.

The following steps S118-S126 being similar to steps S916-S924 of FIG. 9are not repeated here.

Fifth Embodiment

Referring to FIG. 14, a semiconductor package according to a fifthembodiment of the invention is shown. In the fifth embodiment, the samedesignations are used for elements similar to the fourth embodiment, andare not repeated here. The semiconductor package 100 of fifth embodimentdiffers with the semiconductor package 500 of the fourth embodiment inthat the semiconductor package 100 further includes an insulation layer134, preferably a soldermask layer or a polyimide layer.

Preferably, the insulation layer 134 prevents the chip base supportingstud 402 and the trace supporting studs 502 from external pollution lestthe quality of the electrical connection between the semiconductorpackage 100 and external electronic devices might be affected.Preferably, the insulation layer 134 electrically isolates the chip basesupporting stud 402 from an external circuit, such as a circuit board(not illustrated), to avoid the occurrence of short-circuiting betweenthe chip base supporting stud 402 and the external circuit.

Also, referring to FIG. 15, a method flowchart for manufacturingsemiconductor package according to a fifth embodiment of the inventionis shown. As steps S202-S224 being similar to steps S102-S124 of FIG. 12are not repeated here, the following elaboration starts with step S226.

Also, referring to FIG. 16, a semiconductor package of the presentembodiment of the invention with an insulation layer being formed duringthe manufacturing process is shown. In step S226, the insulation layer134 is formed on the surface of the trace molding compound 218 whichexposes the conductive stud lower surface 234, and covers the lowersurfaces 102 of the chip base supporting studs 402 and the lowersurfaces 104 of the trace supporting studs 502. Preferably, theinsulation layer is formed by spin-coating or screen-printing process.Alternatively, it is formed by lithography process. Preferably, theinsulation layer 134 exposes the conductive stud lower surfaces 234 sothat the conductive studs 216 and external circuit can be electricallyconnected.

The following step S228 being similar to step S126 of FIG. 12 is notrepeated here.

Sixth Embodiment

Referring to FIG. 17, a semiconductor package according to a sixthembodiment the invention is shown. In the sixth embodiment, the samedesignations are used for elements similar to the fifth embodiment, andare not repeated here. The semiconductor package 150 of the sixthembodiment differs with the semiconductor package 200 of the fifthembodiment in that the semiconductor package 150 includes two insulationlayers 152 and 154, preferably soldermask layers or polyimide layers.

Also, referring to FIG. 18, a method flowchart for manufacturingsemiconductor package according to a sixth embodiment of the inventionis shown.

As steps S1802-S1818 being similar to steps S202S218 of FIG. 15 are notrepeated here, the following elaboration starts with step S1820.

In step S1820, the insulation layer 152 (the insulation layer 152 isillustrated in FIG. 17) is formed on the lower surface 262 of the tracesubstrate 202 which exposes the conductive studs 216, and the insulationlayer 154 is formed on the upper surface 260 of the trace substrate 202which exposes the trace upper surface 214. Preferably, the insulationlayers 152 and 154 are formed by spin-coating or screen-printing.Alternatively, they are formed by lithography process. The insulationlayer 152 and has a plurality of openings 156, each correspondinglyexposing the lower surface 262 of each conductive stud 216. Theinsulation layer 154 and has a plurality of openings 158 correspondinglyexposing the trace pads 248. Thus, the amount of electrolessnickel/immersion gold (ENIG) subsequently used for coating the lowersurface 262 of the conductive studs 216 and the trace upper surface 214is reduced, the trace upper surface 214 is protected and the substraterigidity is enhanced.

The following step S1822-step S1826 being similar to steps S220-S224 ofFIG. 15 are not repeated here.

The following step S1828 being similar to step S228 of FIG. 15 is notrepeated here.

Seventh Embodiment

Referring to FIG. 19, a semiconductor package according to a seventhembodiment of the invention is shown. The semiconductor package 1100 ofseventh embodiment differs with the semiconductor package 200 of thefirst embodiment in that the chip 204 is disposed on the surface of thetrace substrate 1106 which exposes the conductive studs 1102.

The semiconductor package 1100 includes a trace substrate 1106, a chip204, a plurality of wires 1110, preferably gold wire, a chip moldingcompound 1112, preferably molding compound, and an adhesive 236,preferably polymer epoxy.

The trace substrate 1106 includes a plurality of traces 1116, aplurality of conductive studs 1102 and the trace molding compound 1120.Each trace 1116 has a trace upper surface 1126 and a trace lower surface1124 opposite to each other, wherein the conductive studs 1102 have aconductive stud upper surface 1134.

The conductive studs 1102 are formed on the trace upper surface 1126.The trace molding compound 1120 encapsulates the conductive studs 1102and the trace 1116, and exposes the conductive stud upper surface 1134and the trace lower surface 1124. The trace 1116 and the conductivestuds 1102 are preferably made from copper and preferably formed byelectroplating. The adhesive 236 fixes the chip 204 on the surface ofthe trace substrate 1106 which exposes the conductive studs 1102.

Referring to FIG. 20, a method flowchart for manufacturing semiconductorpackage according to a seventh embodiment of the invention is shown.Steps S302-S312 being similar to steps S402-S412 of FIG. 4 are notrepeated here.

In step S314, the chip 204 is disposed on the surface of the tracesubstrate 1106 which exposes the conductive stud upper surface 1134.

In step S316, the chip 204 and the pads 1136 on the conductive studs1102 are electrically connected by a plurality of wires 206.

The following steps S318-S320 being similar to steps S418-S420 of FIG. 4are not repeated here.

Referring to FIG. 21, a semiconductor package according to anotherembodiment of the invention is shown. The semiconductor package 1900 mayinclude a chip 204, a plurality of traces 1116, a plurality of wires1110, a plurality of conductive studs 1102, a plurality of tracesupporting studs 1904, a plurality of pads 1136, a chip base 302 and aplurality of chip base supporting studs 1902. The chip base supportingstuds 1902 are disposed on the lower surface of the chip base 302. Theadhesive 236 fixes the chip 204 on the upper surface of the chip basesupporting stud 302. The trace molding compound (not designated)encapsulates the chip base 302 and chip base supporting stud 1902. Thelower surface of the trace molding compound exposes the lower surface ofthe chip base supporting stud 1902.

The conductive studs 1102 and the trace supporting stud 1904 can bedisposed on the trace 1116. A plurality of wires 1100 electricallyconnects the chip 204 and the pads 1136 on the conductive studs 1102,and further electrically connects the chip 204 and the pads 1906 on thetrace supporting stud 1904.

Eighth Embodiment

Referring to FIG. 22, a bottom view of the semiconductor package of FIG.2A is shown. The conductive studs 216 are arranged along a first borderL1, that is, the conductive studs 216 are arranged in one row. The tracepads 248 are arranged along a second border L2, that is, the trace pads248 are arranged in one row. Preferably, the first border L1 and thesecond border L2 both surround the chip.

Referring to FIG. 23, a bottom view of a semiconductor package accordingto an eighth embodiment of the invention is shown. In the eighthembodiment, the same designations are used for elements similar to thefirst embodiment, and are not repeated here. The semiconductor package600 of the eighth embodiment differs with the semiconductor package 200of the first embodiment in that the conductive studs 216 of thesemiconductor package 600 are arranged in multiple rows.

The conductive studs 216 of the semiconductor package 600 include aplurality of first conductive studs 216(1) and a plurality of secondconductive studs 216(2). The first conductive studs 216(1) are arrangedalong a third border L3, and the second conductive studs 216(2) arearranged along a fourth border L4. The distance D7 from the third borderL3 to the lateral side 222 differs with the distance D8 from the fourthborder L4 to the lateral side 222, so that the conductive studs 216 arearranged in two rows. Preferably, the third border L3 and the fourthborder L4 both surround the chip.

Preferably, as indicated in FIG. 23, the first conductive studs 216(1)and the second conductive studs 216(2) are interlaced.

Preferably, by making the first conductive studs 216(1) and the secondconductive studs 216(2) interlaced, the semiconductor package canaccommodate more conductive studs 216. That is, the number of the I/Ocontacts of the semiconductor package can be greatly increased.

Preferably, the width W1 between two adjacent first conductive studs216(1) differs with the width W2 between two adjacent second conductivestuds 216(2).

In the present embodiment of the invention, the width W1 between twoadjacent first conductive studs 216(1) differs with the width W2 betweentwo adjacent second conductive studs 216(2). However, in otherembodiments, the width W1 can be equal to the width W2, making thedesign of the distribution of the first conductive studs 216(1) and thesecond conductive studs 216(2) more flexible.

Ninth Embodiment

Referring to FIG. 24, a semiconductor package according to a ninthembodiment of the invention is shown. In the ninth embodiment, the samedesignations are used for elements similar to the eighth embodiment, andare not repeated here. The semiconductor package 700 of the ninthembodiment differs with the semiconductor package 600 of the eighthembodiment in that the trace pads 248 of the semiconductor package 700are arranged in multiple rows.

The trace pads 248 of the semiconductor package 700 include a pluralityof first trace pads 248(1) and a plurality of second the trace pads248(2). The first trace pads 248(1) are arranged along a fifth borderL5, and the second the trace pads 248(2) are arranged along a sixthborder L6. The distance D9 from the fifth border L5 to the lateral side222 of the trace molding compound 218 differs with the distance D10 fromthe sixth border L6 to the lateral side 222 of the trace moldingcompound 218, so that the trace pads 248 are arranged in two rows.Preferably, both the fifth border L5 and the sixth border L6 surroundthe chip.

Preferably, as indicated in FIG. 24, the first trace pads 248(1) and thesecond the trace pads 248(2) are interlaced.

Preferably, by making the first trace pads 248(1) and the second thetrace pads 248(2) interlaced, the semiconductor package 700 canaccommodate more trace pads 248. That is, the number of the I/O contactsof the semiconductor package 700 can be greatly increased.

Besides, the width W3 between two adjacent first trace pads 248(1)differs with the width W4 between two adjacent second trace pads 248(2).However, in other embodiments, the width between two adjacent firsttrace pads 248(1) can also be equal to the width between two adjacentsecond trace pads 248(2), making the design of the distribution of thefirst trace pads 248(1) and the second the trace pads 248(2) moreflexible.

Tenth Embodiment

Referring to FIG. 25, a semiconductor package according to a tenthembodiment of the invention is shown. In the tenth embodiment, the samedesignations are used for elements similar to the first embodiment, andare not repeated here. The semiconductor package 900 of the tenthembodiment differs with the semiconductor package 200 of the firstembodiment in that the conductive studs 216 and the trace pads 248 ofthe semiconductor package 900 are irregularly arranged.

To put it in a greater detail, one of the conductive studs 216 (such asthe conductive studs 216(3)) of the semiconductor package 900 and thelateral side 222 of the trace molding compound 218 are separated by afirst distance D1. Another one of the conductive studs 216 (such as theconductive stud 216(4)) and the lateral side 222 of the trace moldingcompound 218 are separated by a second distance D2. The first distanceD1 differs with the second distance D2. That is, the conductive studs216 of the present embodiment of the invention can be irregularlyarranged.

Preferably, one of the trace pads 248 (such as the trace pads 248(3))and the lateral side 222 of the trace molding compound 218 are separatedby a third distance D3, and another trace pad 248 (such as the trace pas248(4)) and the lateral side 222 are separated by a fourth distance D4.The third distance D3 differs with the fourth distance D4. That is, thetrace pads 248 of the present embodiment of the invention can beirregularly arranged.

According to the foregoing disclosure of the sixth embodiment to theninth embodiment, the conductive studs and the trace are preferablyformed by electroplating, so the traces can be arbitrarily extended andthe conductive studs can be arranged in many different patterns suchthat the flexibility in the design of the semiconductor package of theinvention is increased.

The semiconductor package disclosed in the above embodiments of theinvention have many advantages exemplified below:

(1). The trace supporting studs enhances the rigidity of the trace.Therefore, during the process of wire-bonding the wires on the tracepads of the trace, the trace will not be overbent and deformed due tothe force applied by a wiring tool, hence improving the quality ofwire-bonding.

(2). As the conductive studs are interlaced, the semiconductor packagecan accommodate more conductive studs. That is, the number of the I/Ocontacts of the semiconductor package is greatly increased.

(3). The conductive studs and the trace pads can be arranged in manyrows, so that the number of the I/O contacts of the semiconductorpackage greatly increases.

(4). As the conductive studs and the trace are preferably formed by wayof electroplating, the trace can be arbitrarily extended and theconductive studs can be arranged in many patterns, making the design ofthe semiconductor package more flexible.

(5). The trace pads are disposed near the chip, so that the wireconnects the chip and the trace pads via a shortest distance to avoidthe wires 206 being short-circuited.

(6). As the trace pads are no more limited to be disposed on theperipheral of the semiconductor package, the number of the I/O contactsof the semiconductor package can be greatly increased.

(7). The trace pads and the conductive studs are protected inside themolding compound, and will not be eroded easily.

(8). The trace and the conductive studs are preferably formed by way ofelectroplating. In comparison to the generally known lead frame, thetraces and the conductive studs have smaller sizes and volumes. Thus,the semiconductor package of the invention is conformed to the trend oflightweight, compactness and slimness.

While the invention has been described by way of example and in terms ofa preferred embodiment, it is to be understood that the invention is notlimited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures.

What is claimed is:
 1. A semiconductor package, comprising: a tracemolding compound layer having a first surface and a second surfaceopposite the first surface, wherein the trace molding compound layerencapsulates a plurality of traces and studs between the first andsecond surface of the trace molding compound layer, each of theplurality of traces having a trace upper surface and a trace lowersurface opposite the trace upper surface, each of the plurality of studshaving a stud upper surface and a stud lower surface opposite the studupper surface, the trace upper surface is exposed on the first surfaceof the trace molding compound layer, the stud lower surface is exposedon the second surface of the trace molding compound layer and the studupper surface adjoins the trace lower surface within the trace moldingcompound layer; and a chip molding compound layer having a first surfaceand a second surface opposite the first surface, wherein the chipmolding compound layer encapsulates at least one semiconductor chipbetween the first and second surface of the chip molding compoundlayer;— wherein the chip molding compound layer is disposed on the tracemolding compound layer, the second surface of the chip molding compoundlayer adheres to the first surface of the trace molding compound layerand the trace upper surface, and the chip molding compound layer and thetrace molding compound layer comprise substantially the same moldingcompound material.
 2. The semiconductor package according to claim 1,further comprising: a plurality of trace pads, wherein each trace padcorresponds to one trace and is disposed on the trace upper surface. 3.The semiconductor package according to claim 2, wherein the studs aredisposed a distance away from the corresponding trace pads.
 4. Thesemiconductor package according to claim 2, wherein the studs aredisposed opposite to the corresponding trace pads.
 5. The semiconductorpackage according to claim 2, further comprising: a plurality of tracesupporting studs, each having a trace supporting stud upper surface anda trace supporting the stud lower surface opposite the trace supportingstud upper surface; wherein each trace supporting stud corresponds toone trace pad and is disposed on the trace lower surface opposite thecorresponding trace pad; wherein the trace molding compound layerfurther encapsulates the trace supporting studs, the trace supportingstud upper surface adjoins the trace lower surface and extends to thesecond surface of the trace molding compound layer.
 6. The semiconductorpackage according to claim 5, further comprising: an insulation layerdisposed on the second surface of the trace molding compound layer andthe trace supporting the stud lower surfaces, and exposing the tracesupporting the stud lower surfaces through a plurality of openings inthe insulation layer.
 7. The semiconductor package according to claim 2,further comprising: a chip base, having a chip base upper surface and achip base lower surface opposite the chip base upper surface; whereinthe trace molding compound layer further encapsulates the chip base, thechip base extends from the first surface of the trace molding compoundlayer towards the second surface of the trace molding compound layer,the semiconductor chip is disposed on the chip base.
 8. Thesemiconductor package according to claim 7, further comprising: aplurality of chip base supporting studs, having a chip base supportingstud upper surface and a chip base supporting stud lower surface, eachchip base supporting stud is disposed on the chip base lower surface;wherein the trace molding compound layer further encapsulates the chipbase supporting studs, the chip base supporting stud upper surfaceadjoins the chip base lower surface and extends to the second surface ofthe trace molding compound layer.
 9. The semiconductor package accordingto claim 8, further comprising: an insulation layer disposed on thesecond surface of the trace molding compound layer and the chip basesupporting stud lower surfaces, and exposing the chip base supportinglower surfaces through a plurality of openings in the insulation layer.10. The semiconductor package according to claim 2, further comprising:an insulation layer disposed between the lower surface of the chipmolding compound layer and the upper surface of the trace moldingcompound layer, wherein the insulation layer has a plurality of openingscorresponding to and exposing the trace pads.
 11. The semiconductorpackage according to claim 7, further comprising: an insulation layerdisposed between the lower surface of the chip molding compound layerand the upper surface of the trace molding compound layer, wherein theinsulation layer has a plurality of openings corresponding to andexposing the trace pads and the chip base.
 12. The semiconductor packageaccording to claim 2, wherein the trace pads are arranged surroundingthe semiconductor chip and the studs are arranged below thesemiconductor chip, the trace pads and the lateral side of the tracemolding compound layer are separated by a first distance, the studs andthe lateral side of the trace molding compound layer are separated by asecond distance, and the first distance differs with the seconddistance.
 13. The semiconductor package according to claim 2, whereinthe studs are arranged along a first border surrounding thesemiconductor chip and the trace pads are arranged along a second bordersurrounding the semiconductor chip; wherein the distance of the firstborder to the lateral side of the trace molding compound layer differsfrom the distance of the second border to the lateral side of the tracemolding compound layer.
 14. The semiconductor package according to claim2, wherein the studs comprise a plurality of first studs and a pluralityof second studs, the first studs are arranged surrounding thesemiconductor chip and the second studs are arranged below thesemiconductor chip.
 15. The semiconductor package according to claim 7,wherein the trace pads are arranged surrounding the semiconductor chipand the studs are arranged below the semiconductor chip, the trace padsand the lateral side of the trace molding compound layer are separatedby a first distance, the studs and the lateral side are separated by asecond distance, and the first distance differs with the seconddistance.
 16. The semiconductor package according to claim 7, whereinthe studs are arranged along a first border surrounding the chip baseand the trace pads are arranged along a second border surrounding thechip base; wherein the distance of the first border to the lateral sideof the trace molding compound layer differs from the distance of thesecond border to the lateral side of the trace molding compound layer.17. The semiconductor package according to claim 7, wherein the studscomprise a plurality of first studs and a plurality of second studs, thefirst studs are arranged surrounding the semiconductor chip and thesecond studs are arranged below the semiconductor chip.
 18. Asemiconductor package, comprising: a trace molding compound layer havinga first surface and a second surface opposite the first surface, whereinthe trace molding compound layer encapsulates a plurality of traces andstuds between the first and second surface of the trace molding compoundlayer to form part of or whole of a trace substrate, and the pluralityof traces and studs connect the first surface of the trace moldingcompound layer to the second surface of the trace molding compoundlayer; and a chip molding compound layer having a first surface and asecond surface opposite the first surface, wherein the chip moldingcompound layer encapsulates at least one semiconductor chip between thefirst and second surface of the chip molding compound layer to form achip substrate; wherein the chip substrate is disposed on the tracesubstrate, the second surface of the chip molding compound layer adheresto the first surface of the trace molding compound layer, and the chipmolding compound layer and the trace molding compound layer comprisesubstantially the same molding compound material.